PIC32MX440F256H-80I Datasheet, PDF (480/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
EXAMPLE 21-1: UPDATING THE RTCC TIME AND DATE
/*
The following code example will update the RTCC time and date.
*/
// assume the secondary oscillator is enabled and ready, i.e.
// OSCCON<1>=1, OSCCON<22>=1, and RTCC write is enabled i.e.
// RTCWREN (RTCCON<3>) =1;
unsigned long time=0x04153300;// set time to 04 hr, 15 min, 33 sec
unsigned long date=0x06102705;// set date to Friday 27 Oct 2006
RTCCONCLR=0x8000;
while(RTCCON&0x40);
RTCTIME=time;
RTCDATE=date;
RTCCONSET=0x8000;
while(!(RTCCON&0x40));
// turn off the RTCC
// wait for clock to be turned off
// safe to update the time
// update the date
// turn on the RTCC
// wait for clock to be turned on
// can disable the RTCC write
EXAMPLE 21-2: UPDATING THE RTCC TIME USING THE RTCSYNC WINDOW
/*
The following code example will update the RTCC time and date.
*/
// assume RTCC write is enabled i.e. RTCWREN (RTCCON<3>) =1;
unsigned long time=0x04153300;// set time to 04 hr, 15 min, 33 sec
unsigned long date=0x06102705;// set date to Friday 27 Oct 2006
// disable interrupts, critical section follows
asm volatile (“di”);
while((RTCCON&0x4)!=0);
// wait for not RTCSYNC
RTCTIME=time;
// safe to update the time
RTCDATE=date;
// update the date
// restore interrupts, critical section ended
asm volatile (“ei”);
// can disable the RTCC write
21.2.3 WRITE LOCK
In order to perform a write to any of the RTCC Time reg-
isters, the RTCWREN bit (RTCCON<3>) must be set.
Setting of the RTCWREN bit is only allowed once the
device level unlocking sequence has been executed.
The unlocking sequence is as follows:
1. Suspend or disable all initiators that can access
the peripheral bus and interrupt the unlock
sequence. (i.e., DMA and Interrupts).
2. Store 0xAA996655 to the SYSKEY register.
3. Store 0x556699AA to the SYSKEY register.
4. Set RTCWREN bit into the RTCCON register.
5. Perform the device relock by writing a dummy
value to the SYSKEY register.
6. Re-enable DMA and interrupts.
Note that steps 2 through 4 must be followed exactly to
unlock RTCC write operations. If the sequence is not
followed exactly, the RTCWREN bit will not be set.
Refer to Example 21-3 for a “C” language
implementation of the write unlock operation.
DS61143E-page 478
Preliminary
© 2008 Microchip Technology Inc.