PIC32MX440F256H-80I Datasheet, PDF (411/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

18.0 INTER-INTEGRATED CIRCUIT
(I²C™)
Note:
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive refer-
ence source. Refer to the “PIC32MX Family
Reference Manual” (DS61132) for a
detailed description of this peripheral.
The Inter-Integrated Circuit (I²C) module provides
complete hardware support for both Slave and Multi-
Master modes of the I²C serial communication
standard. Figure 18-1 shows the I²C module block
diagram.
The PIC32MX3XX/4XX devices have up to two I²C
interface modules, denoted as I2C1 and I2C2. Each
I²C module has a 2-pin interface: the SCLx pin is clock
and the SDAx pin is data.
Each I²C module ‘I2Cx’ (x = 1 or 2) offers the following
key features:
• I²C Interface Supporting both Master and Slave
Operation.
• I²C Slave Mode Supports 7 and 10-bit Address.
• I²C Master Mode Supports 7 and 10-bit Address.
• I²C Port allows Bidirectional Transfers between
Master and Slaves.
• Serial Clock Synchronization for I²C Port can be
used as a Handshake Mechanism to Suspend
and Resume Serial Transfer (SCLREL control).
• I²C Supports Multi-master Operation; Detects Bus
Collision and Arbitrates Accordingly.
• Provides Support for Address Bit Masking.
18.1 Operating Modes
The hardware fully implements all the master and slave
functions of the I²C Standard and Fast mode
specifications, as well as 7 and 10-bit addressing.
The I²C module can operate either as a slave or a
master on an I²C bus.
The following types of I²C operation are supported:
• I²C Slave Operation with 7 or 10-bit Address
• I²C Master Operation with 7 or 10-bit Address
For details about the communication sequence in each
of these modes, please refer to the “PIC32MX3XX/4XX
Reference Manual” (DS61132).
PIC32MX3XX/4XX
18.2 I²C Registers
The I2CxCON register allows control of the module’s
operation. The I2CxCON register is readable and writ-
able. I2CxSTAT register contains status flags indicating
the module’s state during operation.
I2CxRCV is the receive register. When the incoming
data is shifted completely, it is moved to the I2CxRCV
register. I2CxTRN is the transmit register to which
bytes are written during a transmit operation.
The I2CxADD register holds the slave address. A
Status bit, ADD10, indicates 10-bit Addressing mode.
The I2CxBRG acts as the Baud Rate Generator (BRG)
reload value.
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV
and an interrupt pulse is generated. The I2CxRSR shift
register is not directly accessable to the programmer.
18.3 I²C Interrupts
The I²C module generates three interrupt signals:
Slave Interrupt (I2CxSIF), Master Interrupt (I2CxMIF)
and Bus Collision Interrupt (I2CxBIF).
18.4 Baud Rate Generator
In I²C Master mode, the reload value for the Baud Rate
Generator (BRG) resides in the I2CxBRG register.
When the BRG is loaded with this value, the BRG
counts down to ‘0’ and stops until another reload has
taken place. If clock arbitration is taking place, for
instance, the BRG is reloaded when the SCLx pin is
sampled high.
As per the I²C standard, FSCL may be 100 kHz or
400 kHz. However, the user can specify any baud rate
up to 1 MHz. I2CxBRG values of ‘0’ or ‘1’ are illegal.
EQUATION 18-1: SERIAL CLOCK RATE
[ ] ^{I2CxBRG =}
PBCLK
FSCL x 2
-2
PBCLK is the peripheral clock speed. FSCL is the
desired I²C bus speed.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 409