PIC32MX440F256H-80I Datasheet, PDF (179/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
9.0 PREFETCH CACHE
Note:
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive refer-
ence source. Refer to the “PIC32MX Family
Reference Manual” (DS61132) for a
detailed description of this peripheral.
The Prefetch cache increases performance for appli-
cations executing out of the cacheable program flash
memory region by implementing instruction caching,
data caching and instruction prefetching.
9.1 Features
• 16 Fully Associative Lockable Cache Lines
• 16-byte Cache Lines
• Up to 4 Cache Lines allocated to Data
• 2 Cache Lines with Address Mask to hold
repeated instructions
• Pseudo LRU replacement policy
• All Cache Lines are software writable
• 16-byte parallel memory fetch
• Predictive Instruction Prefetch
FIGURE 9-1:
PREFETCH MODULE BLOCK DIAGRAM
FSM
CTRL
CTRL
Bus Ctrl
Cache Ctrl
Prefetch Ctrl
Hit LRU
Miss LRU
Tag Logic
Cache
Line
Address
Encode
Cache Line
Hit Logic
P_Prr_eeT_-Fa_Feg_et_tc_ch_h
P^Pr^re^e-^FF^ee^tt^cch^h
RDATA
PFM
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 177