PIC32MX440F256H-80I Datasheet, PDF (457/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
20.3 Master Mode Timing
A PMP Master mode cycle time is defined as the num-
ber of PBCLK cycles required by the PMP to perform a
read or write operation and is dependent on PBCLK
clock speed, PMP address/data multiplexing modes
and the number of PMP wait states, if any. Refer to the
PIC32MX Family Reference Manual, PMP Chapter, for
various timing diagrams. For specific setup and hold
timing characteristics, refer to Section 30.2 “AC Char-
acteristics and Timing Parameters” in this data
sheet.
A PMP master mode read or write cycle is initiated by
accessing (reading or writing) the PMDIN register. Sec-
tion TABLE 20-7: “PMP Read/Write Cycle Times”
below provides a summary of read and write PMP cycle
times for each multiplex configuration.
TABLE 20-7: PMP READ/WRITE CYCLE TIMES
Address/Data Multiplex Configuration
Note:
Demultiplexed
Partial Multiplex
Full Multiplexed (8-bit data)
Full Multiplexed (16-bit data)
Wait states are not enabled
20.3.1 MASTER PORT CONFIGURATION
The Master mode configuration is determined primarily
by the interface requirements to the external device.
Address multiplexing, control signal polarity, data width
and Wait states typically dictate the specific configura-
tion of the PMP master port.
The following illustrates example settings for Master
Mode 2 operation:
• Select Master Mode 2 -
MODE<1:0> (PMMODE<9:8>) = 10.
• Select 16-bit Data mode -
MODE16 (PMMODE<10>) = 1.
• Select partial multiplexed addressing -
ADRMUX<1:0> (PMCON<12:11>) = 01.
• Select auto-address increment -
INCM<1:0> (PMMODE<12:11>) = 01.
• Enable Interrupt Request mode -
IRQM<1:0> (PMMODE<14:13>) = 01.
• Enable PMRD strobe -
PTRDEN (PMCON<8>) = 1.
• Enable PMWR strobe -
PTWREN (PMCON<9>) = 1.
• Enable PMCS2 and PMCS1 Chip Selects -
CSF (PMCON<7:6>) = 10.
• Select PMRD “active-low” pin polarity -
RDSP (PMCON<0>) = 0.
The actual data rate of the PMP (the rate which user’s
code can perform a sequence of read or write opera-
tions) will be highly dependent on several factors:
• a user’s application code content
• code optimization level
• internal bus activity
• other factors relating to the instruction execution
speed.
Note:
During any Master mode read or write
operation, the busy flag will always de-
assert 1 peripheral bus clock cycle
(T_PBCLK), before the end of the operation,
including Wait states. The user’s applica-
tion must check the status of the busy flag
to ensure it is = 0 before initiating the next
PMP operation.
ADRMUX bit
settings
00
01
10
11
PMP Cycle Time
(PBCLK cycles)
Read
Write
2
3
5
6
8
9
5
6
• Select PMWR “active-low” pin polarity -
WRSP (PMCON<1>) = 0.
• Select PMCS2, PMCS1 “active-low” pin polarity -
CS2P (PMCON<4>) = 0 and CS1P
(PMCON<3>) = 0.
• Select 1 wait cycle for data setup -
WAITB<1:0>(PMMODE<7:6>) = 00.
• Select 2 wait cycles to extend PMRD/PMWR -
WAITM<3:0>(PMMODE<5:2>) = 01.
• Select 1 wait cycle for data hold -
WAITB<1:0>(PMMODE<1:0>) = 00.
• Enable upper 8 PMA<15:8> address pins -
PMAEN<15:8> = 1 (lower 8 can be used as
general purpose I/O).
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 455