PIC32MX440F256H-80I Datasheet, PDF (182/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
9.2 Prefetch Registers
REGISTER 9-1: CHECON: CACHE CONTROL REGISTER
r-x
r-x
r-x
r-x
r-x
r-x
r-x
r-x
—
—
—
—
—
—
—
—
bit 31
bit 24
r-x
—
bit 23
r-x
r-x
r-x
r-x
r-x
r-x
R/W-0
—
—
—
—
—
—
CHECOH
bit 16
r-x
—
bit 15
r-x
r-0
r-0
r-x
r-x
R/W-0
R/W-0
—
—
—
—
—
DCSZ<1:0>
bit 8
r-x
—
bit 7
r-x
R/W-0
R/W-0
r-x
R/W-1
R/W-1
R/W-1
—
PREFEN<1:0>
—
PFMWS<2:0>
bit 0
Legend:
R = Readable bit
U = Unimplemented bit
W = Writable bit
P = Programmable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
r = Reserved bit
bit 31-17
bit 16
bit 15-14
bit 13-12
bit 11-10
bit 9-8
bit 7-6
bit 5-4
bit 3
Reserved: Write ‘0’; ignore read
CHECOH: Cache Coherency setting on a PFM Program Cycle bit
1 = Invalidate all data and instruction lines
0 = Invalidate all data lines and instruction lines that are not locked
Reserved: Write ‘0’; ignore read
Reserved: Must be written with zeros
Reserved: Write ‘0’; ignore read
DCSZ<1:0>: Data Cache Size in Lines bits
11 = Enable data caching with a size of 4 Lines
10 = Enable data caching with a size of 2 Lines
01 = Enable data caching with a size of 1 Line
00 = Disable data caching
Changing this field causes all lines to be re-initialized to the “invalid” state.
Reserved: Write ‘0’; ignore read
PREFEN<1:0>: Predictive Prefetch Cache Enable bits
11 = Enable predictive prefetch cache for both cacheable and non-cacheable regions
10 = Enable predictive prefetch cache for non-cacheable regions only
01 = Enable predictive prefetch cache for cacheable regions only
00 = Disable predictive prefetch cache
Reserved: Write ‘0’; ignore read
DS61143E-page 180
Preliminary
© 2008 Microchip Technology Inc.