PIC32MX440F256H-80I Datasheet, PDF (408/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
17.3 SPI Interrupts
The SPI module has the ability to generate interrupts
reflecting the events that occur during the data commu-
nication. The following types of interrupts can be
generated:
• Receive data available interrupts, signalled by
SPI1RXIF (IFS0<25>), SPI2RXIF (IFS1<7>). This
event occurs when there is new data assembled
in the SPIxBUF receive buffer.
• Transmit buffer empty interrupts, signalled by
SPI1TXIF (IFS0<24>), SPI2TXIF (IFS1<6>). This
event occurs when there is space available in the
SPIxBUF transmit buffer and new data can be
written.
• Receive buffer overflow interrupts, signalled by
SPI1EIF (IFS0<23>), SPI2EIF(IFS1<5>).
This event occurs when there is an overflow
condition for the SPIxBUF receive buffer, i.e., new
receive data assembled but the previous one is
not read.
An SPI device is enabled as a source of interrupts via
the respective SPI interrupt enable bits:
• SPI1RXIE (IEC0<25>) and SPI2RXIE (IEC1<7>)
• SPI1TXIE (IEC0<24>) and SPI2TXIE (IEC1<6>)
• SPI1EIE (IEC0<23>) and SPI2EIE (IEC1<5>)
The interrupt priority level bits and interrupt subpriority
level bits must be also be configured:
• SPI1IP (IPC5<28:26>), SPI1IS (IPC5<25:24>)
• SPI2IP (IPC7<28:26>), SPI2IS (IPC7<25:24>)
In addition to enabling the SPI interrupts, an Interrupt
Service Routine, ISR, is required. Example 17-3 is a
partial code example of an ISR.
Note:
It is the user’s responsibility to clear the
corresponding interrupt flag bit before
returning from an ISR.
EXAMPLE 17-3: SPI INITIALIZATION WITH INTERRUPTS ENABLED
/*
The following code example illustrates an SPI1 interrupt configuration.
When the SPI1 interrupt is generated, the cpu will jump to the vector assigned to SPI1
interrupt.
It assumes that none of the SPI1 input pins are shared with an analog input.
If so, the AD1PCFG and corresponding TRIS registers have to be properly configured.
*/
int rData;
IEC0CLR=0x03800000;
SPI1CON = 0;
rData=SPI1BUF;
IFS0CLR=0x03800000;
IPC5CLR=0x1f000000;
IPC5SET=0x0d000000;
IEC0SET=0x03800000;
// disable all SPI interrupts
// Stops and resets the SPI1.
// clears the receive buffer
// clear any existing event
// clear the priority
// Set IPL=3, subpriority 1
// Enable Rx, Tx and Error interrupts
SPI1BRG=0x1;
SPI1STATCLR=0x40;
SPI1CON=0x8220;
// use F_PB/4 clock frequency
// clear the Overflow
// SPI ON, 8 bits transfer, SMP=1, Master Mode
DS61143E-page 406
Preliminary
© 2008 Microchip Technology Inc.