PIC32MX440F256H-80I Datasheet, PDF (232/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
10.4 Pattern Match Termination
The Pattern Match mode is enabled by setting the
PATEN bit (DCHxECON<5>).
This feature is useful in applications where a variable
data size is required and eases the setup of the DMA
channel. A good usage is for transferring ASCII com-
mand strings from an UART, <CR> ended. This is also
useful for implementing string copy routines with DMA
support.
Pattern Match mode features:
• Allows the user to end a transfer if a byte of data
written during a transaction matches a specific
pattern.
• A pattern match is treated the same way as a
block transfer complete, where the CHBCIF
(DCHxINT<3>) bit is set and the CHEN
(DCHxCON<7>) bit is cleared provided
auto-enable CHAEN = 0 (DCHxCON<4>).
• The pattern is stored in the DCHxDAT register.
• If any byte in the source matches DCHxDAT, a
pattern match is detected.
10.4.1 PATTERN MATCH MODE
CONFIGURATION
The Pattern Match mode is an option for use when
performing DMA transfers in basic DMA configuration.
Therefore, the steps needed in Pattern Match mode
are identical to those used in basic DMA configuration.
An extra step is needed to store the desired pattern in
DCHxDAT register.
The following steps are recommended to be taken to
configure a DMA transfer in Pattern Match mode:
• Disable the DMA channel interrupts in the INT
controller.
• Clear any existing channel interrupt flags in the
INT controller.
• Enable the DMA controller (if not already
enabled) in DMACON register.
• Set Channel Control register: Priority,
Auto-Enable mode, etc., in DCHxCON. Don’t
enable the channel yet.
• Set the channel event control: clear/set the events
starting and aborting the transfer. Set the pattern
match enable PATEN in DCHxECON.
• Set the pattern in the DCHxDAT register.
• Set the transfer source and destination physical
addresses (DCHxSSA and DCHxDSA registers).
• Set the source and destination sizes (DCHxSSIZ,
DCHxDSIZ registers).
• Set the cell transfer size (DCHxCSIZ).
• Clear any existing event flag in DCHxINT register.
• If using interrupts:
- Set the conditions that will generate an inter-
rupt in the DCHxINT register (at least error
interrupt enable and abort interrupt enable,
usually block complete interrupt).
- Set the DMA channel interrupt priority and
subpriority in the INT controller.
- Enable the DMA channel interrupt in the INT
controller.
• Enable the selected DMA channel with CHEN
(DCHxCON<7>).
• If not using system events to start the DMA
transfer use CFORCE (DCHxECON<7>) to start
transfer.
• Until the DMA transfer is complete, you can do
some other processing.
• If you enabled transfer complete interrupts (cell
complete, block complete, etc) you’ll be notified in
the ISR that the DMA transfer completed.
• Otherwise, you can poll the DMA channel to see if
the transfer is completed using, for example,
CHBCIF (DCHxINT<3>).
Refer to Example 10-2.
DS61143E-page 230
Preliminary
© 2008 Microchip Technology Inc.