PIC32MX440F256H-80I Datasheet, PDF (353/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
14.3.7 32-BIT SYNCHRONOUS EXTERNAL
CLOCK COUNTER/TIMER MODE
In this mode, T32 (TxCON<3>) = 1 and the timer clock
source is an external clock source or pulse applied to
the TxCK pin, TCS (TxCON<1>) = 1. The 32-bit TMRxy
Count register increments on every synchronized rising
edge of an external clock when the timer clock prescale
<TCKPS> is 1:1.
Note: TxCK pins not available on 64-pin devices.
The timer generates a timer match event after the
TMRxy Count register matches the PRxy register
value, then resets to 0x00000000 on the next external
clock cycle. The timer continues to increment and
repeat the period match until the timer is disabled. For
further details regarding timer events and interrupts,
see Section 14.4 Timer Interrupts.
For clock prescale = N (other than 1:1), the timer
operates at a clock rate = (external clock/N); there-
fore, the TMRxy Count register increments on every
Nth external clock cycle. For further details regarding
timer prescaler, refer to Section 14.3.9 Timer Clock
Prescaler.
The following steps should be performed to properly
configure the 32-bit timer peripheral for Synchronous
Counter mode operation:
1. Clear control bit, ON (TxCON<15>) = 0, to
disable Timer.
2. Set control bit, T32 (TxCON<3>).
3. Select the desired timer prescaler using bits
TCKPS<2:0> (TxCON<6:4>).
4. Set control bit, TCS (TxCON<1>) = 1, to select
an external clock source.
5. Clear Timer register, TMRx.
6. Load Period register, PRx, with desired 32-bit
match value.
7. If timer interrupts are used, refer to Section 14.4
Timer Interrupts for interrupt configuration
steps.
8. Set control bit, ON (TxCON<15>) = 1, to enable
timer.
EXAMPLE 14-5:
32-BIT SYNCHRONOUS
EXTERNAL CLOCK
COUNTER/TIMER
INITIALIZATION
T2CON = 0x0;
//Stop Timer2 and clear
T3CON = 0x0;
//Stop Timer3 and clear
T2CONSET = 0x006A //32-bit mode,
//external clock,
//prescale=1:64
TMR2 = 0x0;
// Clear TMR2 and TMR3
// Same as TMR2 = 0x0
PR2 = 0xFFFFFFFF; // Load PR2 and PR3
// Same as PR2=0xFFFFFFFF
T2CONSET = 0x8000; // Start timer
14.3.8 32-BIT GATED CLOCK
COUNTER/TIMER MODE
In this mode, the timer clock source is the internal
PBCLK (Peripheral Bus Clock), TCS (TxCON<1>) = 0.
The TxCK pin provides the gating mechanism to
enable and disable the timer counting, TGATE
(TxCON<7>) = 1. The 32-bit TMRxy Count register is
enabled on the rising edge of the TxCK pin and incre-
ments on every internal PBCLK cycle when the timer
clock prescale <TCKPS> is 1:1.
Note: TxCK pins not available on 64-pin devices.
The timer increments until the TMRxy Count register
matches the PRxy register value. The TMRxy Count
register resets to 0x00000000 on the next PBCLK clock
cycle. A timer match event is not generated. The timer
continues to increment and repeat the period match
until the falling edge of the TxCK pin or the timer is dis-
abled. On the falling edge of the gate signal, a timer
gate event is generated and the TMRxy Count register
stops counting, but is not reset to 0x00000000. The
TMRxy Count register must be reset in software. For
further details regarding timer events and interrupts,
see Section 14.4 Timer Interrupts.
For clock prescale = N (other than 1:1), the timer oper-
ates at a clock rate = (PBCLK/N); therefore, the TMRxy
Count register increments on every Nth timer clock
cycle. For further details regarding timer prescaler,
refer to Section 14.3.9 Timer Clock Prescaler.
The following steps should be performed to properly
configure the timer peripheral for Gated Timer mode
operation:
1. Clear control bit, ON (TxCON<15>) = 0, to
disable timer.
2. Set control bit, T32 (TxCON<3>).
3. Select the desired timer prescaler using bits
TCKPS<2:0> (TxCON<6:4>).
4. Set control bit, TCS (TxCON<1>) = 0, to select
the internal clock source.
5. Set control bit, TGATE (TxCON<7>) = 1.
6. Clear Timer register, TMRx.
7. Load Period register, PRx, with desired 32-bit
match value.
8. Set control bit, ON (TxCON<15>) = 1, to enable
timer.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 351