PIC32MX440F256H-80I Datasheet, PDF (174/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
8.6 Interrupt Processing
When the priority of a requested interrupt is greater
than the current CPU priority, the interrupt request is
taken and the CPU branches to the vector address
associated with the requested interrupt. Depending on
the priority of the interrupt, the prologue and epilogue
of the interrupt handler must perform certain tasks
before executing any useful code. The following
examples provide recommended prologues and
epilogues.
8.6.1
INTERRUPT PROCESSING IN
SINGLE VECTOR MODE
When the interrupt controller is configured in Single
Vector mode, all of the interrupt requests are serviced
at the same vector address. The interrupt handler
routine must generate a prologue and an epilogue to
properly configure, save and restore all of the core reg-
isters, along with General Purpose Registers. At a
worst case, all of the modifiable General Purpose Reg-
isters must be saved and restored by the prologue and
epilogue.
8.6.1.1 Single Vector Mode Prologue
When entering the interrupt handler routine, the inter-
rupt controller must first save the current priority and
exception PC counter from Interrupt Priority bits, IPLx
(Status<15:10>), and the ErrorEPC register, respec-
tively, on the stack. (Status and ErrorEPC are CPU reg-
isters.) If the routine is presented a new register set, the
previous register set’s stack register must be copied to
the current set’s stack register. Then, the requested pri-
ority may be stored in the IPLx from the Requested
Interrupt Priority bits, RIPLx (Cause<15:10>), Excep-
tion Level bit, EXL, and Error Level bit, ERL, in the Sta-
tus register (Status<1> and Status<2>) are cleared and
the Master Interrupt Enable bit (Status<0>) is set.
Finally, the General Purpose Registers will be saved on
the stack. (The Cause and Status registers are located
in the CPU.)
EXAMPLE 8-5:
SINGLE VECTOR
INTERRUPT HANDLER
PROLOGUE IN ASSEMBLY
CODE
rdpgpr sp, sp
mfc0 k0, Cause
mfc0 k1, EPC
srl k0, k0, 0xa
addiu sp, sp, -76
sw
k1, 0(sp)
mfc0 k1, Status
sw
k1, 4(sp)
ins k1, k0, 10, 6
ins k1,zero, 1, 4
mtc0 k1, Status
sw
s8, 8(sp)
sw
a0, 12(sp)
sw
a1, 16(sp)
sw
a2, 20(sp)
sw
a3, 24(sp)
sw
v0, 28(sp)
sw
v1, 32(sp)
sw
t0, 36(sp)
sw
t1, 40(sp)
sw
t2, 44(sp)
sw
t3, 48(sp)
sw
t4, 52(sp)
sw
t5, 56(sp)
sw
t6, 60(sp)
sw
t7, 64(sp)
sw
t8, 68(sp)
sw
t9, 72(sp)
addu s8, sp, zero
// start interrupt handler code here
DS61143E-page 172
Preliminary
© 2008 Microchip Technology Inc.