PIC32MX440F256H-80I Datasheet, PDF (235/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
EXAMPLE 10-3: CONFIGURING THE DMA FOR CHAINING MODE OPERATION
/*
The following code example illustrates the DMA channel 0 configuration for data transfer
with pattern match enabled. DMA channel 0 transfer from the UART1 to a RAM buffer while DMA
channel 1 transfers data from the RAM buffer to UART2. Transferred strings are at most 256
characters long. Transfer on UART2 will start as soon as the UART1 transfer is completed.
*/
unsigned char myBuff<256>; // transfer buffer
IEC1CLR=0x00010000;
IFS1CLR=0x00010000;
// disable DMA channel 0 interrupts
// clear any existing DMA channel 0 interrupt flag
DMACONSET=0x00008000;
// enable the DMA controller
DCH0CON=0x3;
DCH1CON=0x62;
// channel 0 off, priority 3, no chaining
// channel 1 off, priority 2
// chain to higher priority
// (ch 0), enable events detection while disabled
DCH0ECON=(27 <<8)| 0x30;
DCH1ECON=(42 <<8)| 0x30;
// start irq is UART1 RX, pattern enabled
// start irq is UART1 TX, pattern enabled
DCH0DAT=DCH1DAT=’\r’;
// pattern value, carriage return
DCH0SSA=VirtToPhys(&U1RXREG);
DCH0DSA=VirtToPhys(myBuff);
DCH0SSIZ=1;
DCH0DSIZ=0;
DCH0CSIZ=1;
// program channel 0 transfer
// transfer source physical address
// transfer destination physical address
// source size is 1 byte
// dst size at most 256 bytes
// one byte per UART transfer request
DCH1SSA=VirtToPhys(myBuff);
DCH1DSA=VirtToPhys(&U2TXREG);
DCH1SSIZ=0;
DCH1DSIZ=1;
DCH1CSIZ=1;
// program channel 1 transfer
// transfer source physical address
// transfer destination physical address
// source size at most 256 bytes
// dst size is 1 byte
// one byte per UART transfer request
DCH0INTCLR=0x00ff00ff;
DCH1INTCLR=0x00ff00ff;
DCH1INTSET=0x00090000;
// DMA0: clear events, disable interrupts
// DMA1: clear events, disable interrupts
// DMA1: enable Block Complete and error interrupts
IPC9CLR=0x00001f1f;
IPC9SET=0x00000b16;
IEC1SET=0x00020000;
// clear the DMA channels 0 and 1 priority and
// subpriority
// set IPL 5, subpriority 2 for DMA channel 0
// set IPL 2, subpriority 3 for DMA channel 1
// enable DMA channel 1 interrupt
DCH0CONSET=0x80;
// turn channel on
// do something else
// the UART1 RX interrupts will initiate the DMA channel 0 transfer
// once this transfer is complete, the DMA channel 1 will start
// upon DMA channel 1 transfer completion will get an interrupt
while(!intCh1occurred);
// poll DMA channel 1 interrupt
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 233