PIC32MX440F256H-80I Datasheet, PDF (399/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
17.2.4 FRAMED SPI MODES
The module supports a very basic framed SPI protocol
while operating in either Master or Slave modes. The
following features are provided in the SPI module to
support Framed SPI modes:
• The control bit, FRMEN (SPIxCON<31>), enables
Framed SPI mode and causes the SSx pin to be
used as a frame synchronization pulse input or
output pin. The state of the SSEN (SPIxCON<7>)
is ignored.
• The control bit, FRMSYNC (SPIxCON<30>),
determines whether the SSx pin is an input or an
output (i.e., whether the module receives or
generates the frame synchronization pulse).
• The FRMPOL (SPIxCON<29>) determines the
frame synchronization pulse polarity for a single
SPI clock cycle.
The following framed SPI modes are supported by the
SPI module:
• Frame Master mode: The SPI module generates
the frame synchronization pulse and provides this
pulse to other devices at the SSx pin.
• Frame Slave mode: The SPI module uses a frame
synchronization pulse received at the SSx pin.
The Framed SPI modes are supported in conjunction
with the Master and Slave modes. Thus, the following
framed SPI configurations are available:
• SPI Master mode and Frame Master mode
• SPI Master mode and Frame Slave mode
• SPI Slave mode and Frame Master mode
• SPI Slave mode and Frame Slave mode
These four modes determine whether or not the SPI
module generates the serial clock and the frame
synchronization pulse.
FIGURE 17-5:
SPI MASTER, FRAME MASTER CONNECTION DIAGRAM
PIC32MX3XX/4XX
[SPI Master, Frame Master]
SDOx
Serial Receive Buffer
(SPIxRXB)⁽³⁾
PROCESSOR 2
[SPI Slave, Frame Slave]
SDIx
Serial Receive Buffer
(SPIxRXB)
Shift Register
(SPIxSR)
MSb
LSb
SDIx
SDOx
Shift Register
(SPIxSR)
MSb
LSb
Serial Transmit Buffer
(SPIxTXB)⁽³⁾
Serial Transmit Buffer
(SPIxTXB)
SPI Buffer
(SPIxBUF)
Serial Clock
SCKx
SCKx
SSx _{Frame Sync}
SSx
Pulse^{(1, 2)}
SPI Buffer
(SPIxBUF)
Note 1: In Framed SPI modes, the SSx pin is used to transmit/receive the frame synchronization pulse.
2: Framed SPI modes require the use of all four pins, i.e., using the SSx pin is not optional.
3: The SPIxTXB and SPIxRXB registers are memory mapped to the SPIxBUF register.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 397