PIC32MX440F256H-80I Datasheet, PDF (391/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
REGISTER 17-2: SPIXSTAT: SPI STATUS REGISTER
r-x
r-x
r-x
r-x
r-x
r-x
r-x
r-x
—
—
—
—
—
—
—
—
bit 31
bit 24
r-x
—
bit 23
r-x
r-x
r-x
r-x
r-x
r-x
r-x
—
—
—
—
—
—
—
bit 16
r-x
—
bit 15
r-x
r-x
r-x
R-0
r-x
r-x
r-x
—
—
—
SPIBUSY
—
—
—
bit 8
r-x
—
bit 7
R/W-0
r-x
SPIROV
—
r-x
R-0
r-x
—
SPITBE
—
r-x
R-0
—
SPIRBF
bit 0
Legend:
R = Readable bit
U = Unimplemented bit
W = Writable bit
P = Programmable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
r = Reserved bit
bit 31-12
bit 11
bit 10-7
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
Reserved: Write ‘0’; ignore read
SPIBUSY: SPI Activity Status bit
1 = SPI peripheral is currently busy with some transactions
0 = SPI peripheral is currently idle
Reserved: Write ‘0’; ignore read
SPIROV: Receive Overflow Flag bit
1 = A new data is completely received and discarded. The user software has not read the previous
data in the SPIxBUF register.
0 = No overflow has occurred
This bit is set in hardware; can only be cleared (= 0) in software.
Reserved: Write ‘0’; ignore read
SPITBE: SPI Transmit Buffer Empty Status bit
1 = Transmit buffer, SPIxTXB is empty
0 = Transmit buffer, SPIxTXB is not empty
Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR.
Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB.
Reserved: Write ‘0’; ignore read
Reserved: Write ‘0’; ignore read
SPIRBF: SPI Receive Buffer Full Status bit
1 = Receive buffer, SPIxRXB is full
0 = Receive buffer, SPIXRXB is not full
Automatically set in hardware when SPI transfers data from SPIxSR to SPIxRXB.
Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 389