PIC32MX440F256H-80I Datasheet, PDF (95/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

6.0 MEMORY ORGANIZATION
Note:
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive refer-
ence source. Refer to the “PIC32MX Family
Reference Manual” (DS61132) for a
detailed description of this peripheral.
PIC32MX3XX/4XX microcontrollers provides 4 GB of
unified virtual memory address space. All memory
regions including program, data memory, SFRs, and
Configuration registers reside in this address space at
their respective unique addresses. The program and
data memories can be optionally partitioned into user
and kernel memories. In addition, the data memory can
be made executable, allowing PIC32MX3XX/4XX to
execute from data memory.
Key Features:
• 32-bit native data width
• Separate User and Kernel mode address space
• Flexible program Flash memory partitioning
• Flexible data RAM partitioning for data and
program space
• Separate boot Flash memory for protected code
• Robust bus exception handling to intercept
runaway code.
• Simple memory mapping with Fixed Mapping
Translation (FMT) unit
• Cacheable and non-cacheable address regions
PIC32MX3XX/4XX
6.1 PIC32MX3XX/4XX Memory Layout
PIC32MX3XX/4XX microcontrollers implement two
address spaces: Virtual and Physical. All hardware
resources such as program memory, data memory and
peripherals are located at their respective physical
addresses. Virtual addresses are exclusively used by
the CPU to fetch and execute instructions as well as
access peripherals. Physical addresses are used by
peripherals such as DMA and Flash controller that
access memory independently of CPU.
The entire 4 GB virtual address space is divided into
two primary regions – user and kernel space. The lower
2 GB of space forms the User mode segment, called
useg/kuseg. The upper 2 GB of virtual address space
forms the kernel-only space. The kernel space is
divided into four segments of 512 MB each: kseg 0,
kseg 1, kseg 2 and kseg 3. Only Kernel mode applica-
tions can access kernel space memory. The peripheral
registers are only visible through kernel space.
The Fixed Mapping Translation (FMT) unit translates
the memory segments into corresponding physical
address regions. A virtual memory segment may also
be cached, provided the cache module is available on
the device. Please note that the kseg 1 memory seg-
ment is not cacheable, while kseg 0 and useg/kuseg
are cacheable.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 93