PIC32MX440F256H-80I Datasheet, PDF (91/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

5.2.4
WATCHDOG TIMER TIME-OUT
RESET (WDTR)
A Watchdog Timer time-out causes the device Reset,
SYSRST, to be asserted asynchronously. Note that a
WDT time-out during SLEEP or IDLE mode will wake-up
the processor and branch to the PIC32MX3XX/4XX
Reset vector, but not reset the processor. The only bits
affected are WDTO and the SLEEP or IDLE bits in the
RCON register. For more information, refer to Section
26.0 “Watchdog Timer”.
Note:
In this document, a distinction is made
between a power mode as it is used in a
specific module, and a power mode as it is
used by the device, e.g., Sleep mode of the
comparator and SLEEP mode of the CPU.
To indicate which type of power mode is
intended, uppercase and lowercase letters
(Sleep, Idle, Debug) signify a module
power mode, and all uppercase letters
(SLEEP, IDLE, DEBUG) signify a device
power mode.
5.2.5 BROWN-OUT RESET (BOR)
PIC32MX3XX/4XX devices have a simple brown-out
capability. If the voltage supplied to the regulator is inad-
equate to maintain a regulated level, the regulator Reset
circuitry will generate a Brown-out Reset. This event is
captured by the BOR flag bit (RCON<1>). Refer to
Section 30.2 “AC Characteristics and Timing Param-
eters” for further details.
5.2.6
CONFIGURATION MISMATCH
RESET
To maintain the integrity of the stored configuration val-
ues, all device Configuration bits are implemented as a
complementary set of register bits. For each bit, as the
actual value of the register is written as ‘1’, a comple-
mentary value, ‘0’, is stored into its corresponding
background register and vice versa. The bit pairs are
compared every time, including Sleep mode. During
this comparison, if the Configuration bit values are not
found opposite to each other, a Configuration Mismatch
event is generated which causes a device Reset.
If a device Reset occurs as a result of a Configuration
Mismatch, the CM bit (RCON<9>) is set.
PIC32MX3XX/4XX
5.3 Reset States
5.3.1
SPECIAL FUNCTION REGISTER
RESET STATES
Most of the Special Function Registers (SFRs) associ-
ated with the PIC32MX3XX/4XX CPU and peripherals
are reset to a particular value at a device Reset. Refer
to the corresponding data sheet section for a periph-
eral’s SFR details. The Reset value for each SFR will
depend on the type of Reset.
5.3.2
CONFIGURATION WORD
REGISTER RESET STATES
All Reset conditions force the Flash Configuration
Word registers to be re-loaded. However, a POR forces
Flash Configuration Word registers to be reset prior to
being reloaded. For all other Reset conditions, the
Flash Configuration Word registers are not reset prior
to being re-loaded. This difference accommodates
MCLR assertions during Debug mode without affecting
the state of the debug operations.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 89