PIC32MX440F256H-80I Datasheet, PDF (402/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
17.2.4.4 SPI Master Mode and Frame Slave
Mode Operations
This Framed SPI mode is enabled by setting bits
MSTEN (SPIxCON<5>), FRMEN (SPIxCON<31>),
and FRMSYNC (SPIxCON<30>) to ‘1’. The SSx pin is
an input, and it is sampled on the sample edge of the
SPI clock. When it is sampled active, high, or low
depending on bit FRMPOL (SPIxCON<29>), data will
be transmitted on the subsequent transmit edge of the
SPI clock, as shown in Figure 17-7. The interrupt flag
SPIxIF is set when the transmission is complete. The
user must make sure that the correct data is loaded into
the SPIxBUF for transmission before the signal is
received at the SSx pin. A connection diagram
indicating signal directions for this operating mode is
shown in Figure 17-8.
The SCK and SDO pins are outputs, the SDI and SSx
pins are inputs. Setting the control bit, DISSDO
(SPIxCON<12>), disables transmission at the SDO pin
if Receive Only mode of operation is desired; refer to
Table 17-7.
The SDI pin must be configured to properly sample the
data received from the slave device by configuring the
sample bit, SMP (SPIxCON<9>).
In Master mode, the SCK clock edge and polarity must
be configured properly for the master and slave device
to correctly transfer data synchronously.
Refer to timing diagram shown in Figure 17-3 to
determine the appropriate settings.
17.2.4.5 Master SPIxCON Configuration
The following bits must be configured as shown for the
Master mode of operation when configuring the
SPIxCON register:
• Enable Master Mode –
MSTEN (SPIxCON<5>) = 1
• Enable Framed SPI support –
FRMEN (SPIxCON<31>) = 1
• Select SSx pin as Frame Slave (input) –
FRMSYNC (SPIxCON<30>) = 1
The remaining bits are shown with example
configurations and may be configured as desired:
• Enable module control of SDO pin –
DISSDO (SPIxCON<12>) = 0
• Configure SCK clock polarity to Idle high –
CKP (SPIxCON<6>) = 1
• Configure SCK clock edge transition from Idle to
active – CKE (SPIxCON<8>) = 0
• Select SSx active low pin polarity –
FRMPOL (SPIxCON<29>) = 0
• Select 16-bit data width –
MODE<32,16> (SPIxCON<11:10>) = 01
• Sample data input at middle –
SMP (SPIxCON<9>) = 0
• Enable SPI module when CPU Idle –
SIDL (SPIxCON<13>) = 0
17.2.4.6 Framed Slave Mode Initialization
The following steps are used to set up the SPI module
for the Slave mode of operation:
1. If interrupts are used, disable the SPI interrupts
in the respective IEC0/1 register.
2. Stop and reset the SPI module by clearing the
ON bit.
3. Clear the receive buffer.
4. If using interrupts, the following additional steps
are performed:
• Clear the SPIx interrupt flags/events in the
respective IFS0/1 register.
• Set the SPIx interrupt enable bits in the
respective IEC0/1 register.
• Write the SPIx interrupt priority and
subpriority bits in the respective IPC5/7
register.
5. Clear the SPIROV bit (SPIxSTAT<6>).
6. Write the selected configuration settings to the
SPIxCON register.
7. Enable SPI operation by setting the ON bit
(SPIxCON<15>).
Note 1: The user must turn off the SPI device
prior to changing the CKE or CKP bits.
Otherwise, the behavior of the device is
not ensured.
2: The SPIxSR register cannot be written
into directly by the user. All writes to the
SPIxSR register are performed through
the SPIxBUF register.
3: Receiving a frame sync pulse will start a
transmission, regardless of whether or
not data was written to SPIxBUF. If a
write was not performed, zeros will be
transmitted.
DS61143E-page 400
Preliminary
© 2008 Microchip Technology Inc.