3069RF-ZTAT Datasheet, PDF (99/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

4.3 Interrupts
Interrupt exception handling can be requested by seven external sources (NMI, IRQ₀ to IRQ₅), and
36 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources
and indicates the number of interrupts of each type.
The on-chip supporting modules that can request interrupts are the watchdog timer (WDT),
DRAM interface, 16-bit timer, 8-bit timer, DMA controller (DMAC), serial communication
interface (SCI), and A/D converter. Each interrupt source has a separate vector address.
NMI is the highest-priority interrupt and is always accepted*. Interrupts are controlled by the
interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority
levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt
priority registers A and B (IPRA and IPRB) in the interrupt controller.
Note: * NMI input is sometimes disabled when flash memory is being programmed or erased. For
details see section 18.4.5 Flash Vector Address Control Register (FVACR).
For details on interrupts see section 5, Interrupt Controller.
Interrupts
External interrupts ^{NMI (1)}
IRQ₀ to IRQ₅ (6)
Internal interrupts
WDT^*1 (1)
DRAM interface^*2 (1)
16-bit timer (9)
8-bit timer (8)
DMAC (4)
SCI (12)
A/D converter (1)
Notes: Numbers in parentheses are the number of interrupt sources.
1. When the watchdog timer is used as an interval timer, it generates an interrupt request
at every counter overflow.
2. When the DRAM interface is used as an interval timer, it generates an interrupt request
at compare match.
Figure 4.4 Interrupt Sources and Number of Interrupts
Rev. 5.0, 09/04, page 77 of 978