3069RF-ZTAT Datasheet, PDF (712/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

19.2.2 External Clock Input
When the external clock signal is input to the EXTAL pin, the counter-phase clock signal should
be input to the XTAL pin as shown in figure 19.5 (a). However, the external clock should go high
in standby mode.
When the XTAL pin is left open, the foot pattern on the board should be formed as small as
possible and wiring should not be done on the printed-circuit board in order to make the stray
capacitance at the XTAL pin be the minimum value.
EXTAL
XTAL
External clock input
(a) Complementary clock input at XTAL pin
EXTAL
XTAL
Open
External clock input
(b) XTAL pin left open
Figure 19.5 External Clock Input (Examples)
External Clock: The external clock frequency should be equal to the system clock frequency
when not divided by the on-chip frequency divider. Table 19.3 shows the clock timing, figure
19.6 shows the external clock input timing, and figure 19.7 shows the external clock output
settling delay timing. When the appropriate external clock is input via the EXTAL pin, its
waveform is corrected by the on-chip oscillator and duty adjustment circuit.
When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the
on-chip oscillator and duty adjustment circuit. The resulting stable clock is output to external
devices after the external clock settling time (t_DEXT) has passed after the clock input. The system
must remain reset with the reset signal low during t_DEXT, while the clock output is unstable.
Rev. 5.0, 09/04, page 690 of 978