3069RF-ZTAT Datasheet, PDF (231/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

7.3.4 Data Transfer Control Registers (DTCR)
The data transfer control registers (DTCRs) are 8-bit readable/writable registers that control the
operation of the DMAC channels. A channel operates in full address mode when bits DTS2A and
DTS1A are both set to 1 in DTCRA. DTCRA and DTCRB have different functions in full address
mode.
DTCRA
Bit
Initial value
Read/Write
7
DTE
0
R/W
6
DTSZ
0
R/W
5
SAID
0
R/W
4
SAIDE
0
R/W
3
DTIE
0
R/W
2
DTS2A
0
R/W
1
DTS1A
0
R/W
0
DTS0A
0
R/W
Data transfer enable
Enables or disables
data transfer
Data transfer size
Selects byte or
word size
Data transfer
interrupt enable
Enables or disables the
CPU interrupt at the end
of the transfer
Data transfer
select 0A
Selects block
transfer mode
Source address
increment/decrement
Source address increment/
decrement enable
These bits select whether
the source address register
(MARA) is incremented,
decremented, or held fixed
during the data transfer
Data transfer select
2A and 1A
These bits must both be
set to 1
DTCRA is initialized to H'00 by a reset and in standby mode.
Rev. 5.0, 09/04, page 209 of 978