3069RF-ZTAT Datasheet, PDF (865/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

BCR—Bus Control Register
H'EE024 Bus controller
Bit
Initial value
Read/Write
7
ICIS1
1
R/W
6
5
4
3
2
ICIS0 BROME BRSTS1 BRSTS0 EMC
1
0
0
0
1
R/W
R/W
R/W
R/W
R/W
1
0
RDEA WAITE
1
0
R/W R/W
Wait pin enable
0 9)16 pin wait input is disabled
1 9)16 pin wait input is enabled
Area division unit select
0 Area divisions are as follows:
Area 0: 2 MB Area 4: 1.93 MB
Area 1: 2 MB Area 5: 4 kB
Area 2: 8 MB Area 6: 23.75 kB
Area 3: 2 MB Area 7: 22 B
1 Areas 0 to 7 are the same size
(2 MB)
Expansion memory map control
0
Memory map in figure 3.2 in section 3.6 (Memory Map
in Each Operating Mode)
1
Memory map in figure 3.1 in section 3.6 (Memory Map
in Each Operating Mode)
Burst cycle select 0
0 Max. 4 words in burst access
1 Max. 8 words in burst access
Burst cycle select 1
0 Burst access cycle comprises 2 states
1 Burst access cycle comprises 3 states
Burst ROM enable
0 Area 0 is a basic bus interface area
1 Area 0 is a burst ROM interface area
Idle cycle insertion 0
0 No idle cycle is inserted in case of consecutive external read and write cycles
1 Idle cycle is inserted in case of consecutive external read and write cycles
Idle cycle insertion 1
0 No idle cycle is inserted in case of consecutive external read cycles for different areas
1 Idle cycle is inserted in case of consecutive external read cycles for different areas
Rev. 5.0, 09/04, page 843 of 978