3069RF-ZTAT Datasheet, PDF (245/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

In repeat mode ETCRH is used as the transfer counter while ETCRL holds the initial transfer
count. ETCRH is decremented by 1 at each transfer until it reaches H'00, then is reloaded from
ETCRL. MAR is also restored to its initial value, which is calculated from the DTSZ and DTID
bits in DTCR. Specifically, MAR is restored as follows:
MAR ← MAR – (–1)^DTID · 2^DTSZ · ETCRL
ETCRH and ETCRL should be initially set to the same value.
In repeat mode transfers continue until the CPU clears the DTE bit to 0. After DTE is cleared to 0,
if the CPU sets DTE to 1 again, transfers resume from the state at which DTE was cleared. No
CPU interrupt is requested.
As in I/O mode, MAR and IOAR specify the source and destination addresses. MAR specifies a
24-bit source or destination address. IOAR specifies the lower 8 bits of a fixed address. The upper
16 bits are all 1s. IOAR is not incremented or decremented.
Figure 7.6 illustrates how repeat mode operates.
Address T
Transfer
1 byte or word is
transferred per request
IOAR
Address B
[Legend]
L = initial setting of MAR
N = initial setting of ETCRH and ETCRL
Address T = L
Address B = L + (–1) ^DTID• (2 ^DTSZ • N – 1)
Figure 7.6 Operation in Repeat Mode
Rev. 5.0, 09/04, page 223 of 978