3069RF-ZTAT Datasheet, PDF (133/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Section 6 Bus Controller
6.1 Overview
The H8/3069R has an on-chip bus controller (BSC) that manages the external address space
divided into eight areas. The bus specifications, such as bus width and number of access states,
can be set independently for each area, enabling multiple memories to be connected easily.
The bus controller also has a bus arbitration function that controls the operation of the internal bus
masters-the CPU, DMA controller (DMAC), and DRAM interface and can release the bus to an
external device.
6.1.1 Features
The features of the bus controller are listed below.
• Manages external address space in area units
 Manages the external space as eight areas (0 to 7) of 128 kbytes in 1-Mbyte modes, or 2
Mbytes in 16-Mbyte modes
 Bus specifications can be set independently for each area
 DRAM/burst ROM interfaces can be set
• Basic bus interface
 Chip select (CS₀ to CS₇) can be output for areas 0 to 7
 8-bit access or 16-bit access can be selected for each area
 Two-state access or three-state access can be selected for each area
 Program wait states can be inserted for each area
 Pin wait insertion capability is provided
• DRAM interface
 DRAM interface can be set for areas 2 to 5
 Row address/column address multiplexed output (8/9/10 bits)
 2-CAS byte access mode
 Burst operation (fast page mode)
 T_P cycle insertion to secure RAS precharging time
 Choice of CAS-before-RAS refreshing or self-refreshing
• Burst ROM interface
 Burst ROM interface can be set for area 0
 Selection of two- or three-state burst access
Rev. 5.0, 09/04, page 111 of 978