3069RF-ZTAT Datasheet, PDF (533/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
D = 0.5, F = 0
M = (0.5 – ¹
2 • 16
= 46.875%
) • 100%
. . . . . . . . (2)
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Restrictions on Use of DMAC:
• When an external clock source is used for the serial clock, after the DMAC updates TDR,
allow an inversion of at least five system clock (φ) cycles before input of the serial clock to
start transmitting. If the serial clock is input within four states of the TDR update, a
malfunction may occur (see figure 13.22) .
• To have the DMAC read RDR, be sure to select the corresponding SCI receive-data-full
interrupt (RXI) as the activation source with bits DTS2 to DTS0 in DTCR.
SCK
t
TDRE
D0
D1
D2
D3
D4
D5
D6
D7
Note: In operation with an external clock source, be sure that t >4 states.
Figure 13.22 Example of Synchronous Transmission Using DMAC
Rev. 5.0, 09/04, page 511 of 978