3069RF-ZTAT Datasheet, PDF (163/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Cautions: When using address update modes, the following points should be noted.
• When address update mode 2 is selected, the address in an internal space (on-chip memory or
internal I/O) access cycle is not output externally.
• In order to secure address holding with respect to the rise of RD, when address update mode 2
is used an external space read access must be completed within a single access cycle. For
example, in a word access to 8-bit access space, the bus cycle is split into two as shown in
figure 6.6, and so there is not a single access cycle. In this case, address holding is not
guaranteed at the rise of RD between the first (even address) and second (odd address) access
cycles (area inside the ellipse in the figure).
On-chip
memory cycle
External read cycle
(8-bit space word access)
On-chip
memory cycle
Address update
mode 2
RD
Even address Odd address
Figure 6.6 Example of Consecutive External Space Accesses in Address Update Mode 2
• When address update mode 2 is selected, in a DRAM space CAS-before-RAS (CBR) refresh
cycle the previous address is retained (the area 2 start address is not output).
Rev. 5.0, 09/04, page 141 of 978