3069RF-ZTAT Datasheet, PDF (640/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

No interrupts are accepted during download processing. However, interrupt requests other than
NMI requests are held, so when processing returns to the user procedure program and
interrupts are generated. NMI requests are discarded if the FVACR register value is H'00.
However, if H'80 has been written to the FVACR register, they are held and the NMI
interrupts are generated when processing returns to the user procedure program.
The sources of the interrupt requests from the on-chip module and at the falling edge of the
IRQ are held during downloading. The refresh can be put in the DRAM.
When the level-detection interrupt requests are to be held, interrupts must be put until the
download is ended.
When hardware standby mode is entered during download processing, the normal download
cannot be guaranteed in the on-chip RAM. Therefore, download must be executed again.
Since a stack area of a maximum 128 bytes is used, the area must be saved before setting the
SCO bit to 1.
If flash memory is accessed by the DMAC or BREQ during downloading, the operation
cannot be guaranteed. Therefore, access by the DMAC or BREQ must not be executed.
(d) FKEY is cleared to H'00 for protection.
(e) The value of the DPFR parameter must be checked and the download result must be
confirmed.
A recommended procedure for confirming the download result is shown below.
• Check the value of the DPFR parameter (one byte of start address of the download
destination specified by FTDAR). If the value is H'00, download has been performed
normally. If the value is not H'00, the source that caused download to fail can be
investigated by the description below.
• If the value of the DPFR parameter is the same as before downloading (e.g. H'FF), the
address setting of the download destination in FTDAR may be abnormal. In this case,
confirm the setting of the TDER bit (bit 7) in FTDAR.
• If the value of the DPFR parameter is different from before downloading, check the SS
bit (bit 2) and the FK bit (bit 1) in the DPFR parameter to ensure that the download
program selection and FKEY register setting were normal, respectively.
(f) The operating frequency and user branch destination are set to the FPEFEQ and FUBRA
parameters for initialization.
• The current frequency of the CPU clock is set to the FPEFEQ parameter (general
register: ER0).
Rev. 5.0, 09/04, page 618 of 978