3069RF-ZTAT Datasheet, PDF (715/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

19.5.1 Register Configuration
Table 19.4 summarizes the frequency division register.
Table 19.4 Frequency Division Register
Address*
Name
Abbreviation
R/W
H'EE01B
Division control register DIVCR
R/W
Note: * Lower 20 bits of the address in advanced mode.
Initial Value
H'FC
19.5.2 Division Control Register (DIVCR)
DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency
divider.
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
DIV1 DIV0
Initial value
1
1
1
1
1
1
0
0
Read/Write
—
—
—
—
—
—
R/W R/W
Reserved bits
Divide bits 1 and 0
These bits select the
frequency division ratio
DIVCR is initialized to H'FC by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 2—Reserved: These bits cannot be modified and are always read as 1.
Bits 1 and 0—Divide (DIV1, DIV0): These bits select the frequency division ratio, as follows.
Bit 1
DIV1
0
0
1
1
Bit 0
DIV0
0
1
0
1
Frequency Division Ratio
1/1
1/2
1/4
1/8
(Initial value)
Rev. 5.0, 09/04, page 693 of 978