3069RF-ZTAT Datasheet, PDF (152/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Bit 7
MXC1
0
1
Bit 6
MXC0
0
1
0
1
Description
Column address: 8 bits
Compared address:
Modes 1, 2
8-bit access space
16-bit access space
Modes 3, 4, 5
8-bit access space
16-bit access space
Column address: 9 bits
Compared address:
Modes 1, 2
8-bit access space
16-bit access space
Modes 3, 4, 5
8-bit access space
16-bit access space
Column address: 10 bits
Compared address:
Modes 1, 2
8-bit access space
16-bit access space
Modes 3, 4, 5
8-bit access space
16-bit access space
Illegal setting
A₁₉ to A₈
A₁₉ to A₉
A₂₃ to A₈
A₂₃ to A₉
A₁₉ to A₉
A₁₉ to A₁₀
A₂₃ to A₉
A to A
23
10
A₁₉ to A₁₀
A₁₉ to A₁₁
A to A
23
10
A₂₃ to A₁₁
Bit 5—CAS Output Pin Select (CSEL): Selects the UCAS and LCAS output pins when areas 2
to 5 are designated as DRAM space.
Bit 5
CSEL
0
1
Description
PB4 and PB5 selected as UCAS and LCAS output pins
HWR and LWR selected as UCAS and LCAS output pins
(Initial value)
Bit 4—Refresh Cycle Enable (RCYCE): Enables or disables CAS-before-RAS refresh cycle
insertion. When none of areas 2 to 5 has been designated as DRAM space, refresh cycles are not
inserted regardless of the setting of this bit.
Bit 4
RCYCE
0
1
Description
Refresh cycles disabled
DRAM refresh cycles enabled
(Initial value)
Rev. 5.0, 09/04, page 130 of 978