3069RF-ZTAT Datasheet, PDF (261/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Figure 7.17 shows the timing when the DMAC is activated by level-sensitive low DREQ input in
normal mode.
φ
DREQ
CPU cycle
DMAC cycle
CPU cycle
T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T ₁
Address
bus
RD
HWR , LWR
Minimum 4 states
Next sampling point
Figure 7.17 Timing of DMAC Activation by Low DREQ Level in Normal Mode
Rev. 5.0, 09/04, page 239 of 978