3069RF-ZTAT Datasheet, PDF (427/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

10.7.3 Contention between TCOR Write and Compare Match
If a compare match occurs in the T₃ state of a TCOR write cycle, writing takes priority and the
compare match signal is inhibited. Figure 10.20 shows the timing in this case.
TCOR write cycle
T1
T2
T3
φ
Address bus
TCOR address
Internal write signal
8TCNT
N
N+1
TCOR
Compare match signal
N
M
TCOR write data
Inhibited
Figure 10.20 Contention between TCOR Write and Compare Match
Rev. 5.0, 09/04, page 405 of 978