3069RF-ZTAT Datasheet, PDF (342/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Bit 1—Timer Sync 1 (SYNC1): Selects whether channel 1 operates independently or
synchronously.
Bit 1
SYNC1
0
1
Description
Channel 1’s timer counter (16TCNT1) operates independently
16TCNT1 is preset and cleared independently of other channels
Channel 1 operates synchronously
16TCNT1 can be synchronously preset and cleared
(Initial value)
Bit 0—Timer Sync 0 (SYNC0): Selects whether channel 0 operates independently or
synchronously.
Bit 0
SYNC0
0
1
Description
Channel 0’s timer counter (16TCNT0) operates independently
16TCNT0 is preset and cleared independently of other channels
Channel 0 operates synchronously
16TCNT0 can be synchronously preset and cleared
(Initial value)
9.2.3 Timer Mode Register (TMDR)
TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 2. It also
selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2.
Bit
Initial value
Read/Write
7
6
5
4
—
MDF FDIR
—
1
0
0
1
—
R/W R/W
—
3
2
1
0
— PWM2 PWM1 PWM0
1
0
0
0
—
R/W R/W R/W
Reserved bit
PWM mode 2 to 0
These bits select PWM
mode for channels 2 to 0
Flag direction
Selects the setting condition for the overflow
flag (OVF) in TISRC
Phase counting mode flag
Selects phase counting mode for channel 2
Reserved bit
TMDR is initialized to H'98 by a reset and in standby mode.
Rev. 5.0, 09/04, page 320 of 978