3069RF-ZTAT Datasheet, PDF (260/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Figure 7.16 shows the timing when the DMAC is activated by the falling edge of DREQ in normal
mode.
φ
DREQ
Address
bus
RD
CPU cycle
DMAC cycle
CPU
cycle DMAC cycle
T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂
HWR , LWR
Minimum 4 states
Next sampling point
Figure 7.16 Timing of DMAC Activation by Falling Edge of DREQ in Normal Mode
Rev. 5.0, 09/04, page 238 of 978