3069RF-ZTAT Datasheet, PDF (467/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that
TCNT has overflowed and generated a reset signal. This reset signal resets the entire H8/3069R
chip internally.
Bit 7
WRST
0
1
Description
[Clearing condition]
Reset signal at RES pin.
Read WRST when WRST =1, then write 0 in WRST.
(Initial value)
[Setting condition]
Set when TCNT overflow generates a reset signal during watchdog timer operation
Bit 6—Reserved: The write value should always be 0.
Bits 5 to 0—Reserved: These bits are always read as 1. The write value should always be 1.
12.2.4 Notes on Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write. The procedures for writing and reading these registers are given below.
Writing to TCNT and TCSR: These registers must be written by a word transfer instruction.
They cannot be written by byte instructions. Figure 12.2 shows the format of data written to
TCNT and TCSR. TCNT and TCSR both have the same write address. The write data must be
contained in the lower byte of the written word. The upper byte must contain H'5A (password for
TCNT) or H'A5 (password for TCSR). This transfers the write data from the lower byte to TCNT
or TCSR.
TCNT write
15
Address H'FFF8C *
H'5A
87
0
Write data
TCSR write
15
Address H'FFF8C *
H'A5
87
0
Write data
Note: * Lower 20 bits of the address in advanced mode.
Figure 12.2 Format of Data Written to TCNT and TCSR
Rev. 5.0, 09/04, page 445 of 978