3069RF-ZTAT Datasheet, PDF (258/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Figure 7.14 shows the timing when the DMAC is activated by low input at a DREQ pin. This
example shows a word-size transfer from a 16-bit two-state access area to another 16-bit two-state
access area. The DMAC continues the transfer while the DREQ pin is held low.
CPU cycle
DMAC cycle
CPU cycle
DMAC cycle
(last transfer cycle)
CPU cycle
T₁ T₂ T₃ T_d T₁ T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂ T₁ T₂
φ
DREQ
Address
bus
RD
HWR, LWR
TEND
Source Destination
address address
Source Destination
address address
Figure 7.14 Bus Timing of DMA Transfer Requested by Low DREQ Input
Rev. 5.0, 09/04, page 236 of 978