3069RF-ZTAT Datasheet, PDF (32/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Type
Data bus
Symbol
D₁₅ to D₀
Bus control CS₇ to
CS
0
AS
RD
HWR
LWR
WAIT
DRAM
interface
DMA
controller
(DMAC)
RFSH
CS₂ to
CS
5
RD
HWR
UCAS
LWR
LCAS
DREQ₁,
DREQ₀
TEND₁,
TEND
0
Pin No.
FP-100B
TFP-100B I/O
Name and Function
34 to 23, Input/ Data bus: Bidirectional data bus
21 to 18 output
2 to 5,
Output Chip select: Select signals for areas 7 to 0
88 to 91
69
Output Address strobe: Goes low to indicate valid address
output on the address bus
70
Output Read: Goes low to indicate reading from the external
address space
71
Output High write: Goes low to indicate writing to the
external address space; indicates valid data on the
upper data bus (D to D ).
15
8
72
Output Low write: Goes low to indicate writing to the
external address space; indicates valid data on the
lower data bus (D₇ to D₀).
58
Input Wait: Requests insertion of wait states in bus cycles
during access to the external address space
87
Output Refresh: Indicates a refresh cycle
89, 88,
5, 4
Output Row address strobe RAS: Row address strobe
signal for DRAM
70
Output Write enable WE: Write enable signal for DRAM
71
Output Upper column address strobe UCAS: Column
6
address strobe signal for DRAM
72
Output Lower column address strobe LCAS: Column
7
address strobe signal for DRAM
5, 3
Input DMA request 1 and 0: DMAC activation
requests
94, 93
Output Transfer end 1 and 0: These signals indicate that
the DMAC has ended a data transfer
Rev. 5.0, 09/04, page 10 of 978