3069RF-ZTAT Datasheet, PDF (210/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Bus cycle A
(DRAM access cycle) Bus cycle B
φ
Address bus
Tp Tr Tc1 Tc2 T1 T2
HWR/LWR
(UCAS/LCAS)
CSn
Bus cycle A
(DRAM access cycle) Bus cycle B
Tp Tr Tc1 Tc2 Ti T1 T2
φ
Address bus
HWR/LWR
(UCAS/LCAS)
CSn
Simultaneous change of
HWR/LWR and CSn
(a) Idle cycle not inserted
(b) Idle cycle inserted
Figure 6.45 Example of Idle Cycle Operation (3) (HWR/LWR Used as UCAS/LCAS)
φ
Address bus
RD
UCAS/LCAS
Address bus
External read DRAM space read
T1 T2 T3 Tp Tr Tc1 Tc2
Figure 6.46 Example of Idle Cycle Operation (4) (Consecutive Precharge Cycles)
Usage Notes: When non-insertion of idle cycles is set, the rise (negation) of RD and the fall
(assertion) of CSn may occur simultaneously. An example of the operation is shown in figure
6.47.
If consecutive reads between different external areas occur while the ICIS1 bit is cleared to 0 in
BCR, or if a write cycle to a different external area occurs after an external read while the ICIS0
bit is cleared to 0, the RD negation in the first read cycle and the CSn assertion in the following
bus cycle will occur simultaneously. Therefore, depending on the output delay time of each signal,
it is possible that the low-level output of RD in the preceding read cycle and the low-level output
of CSn in the following bus cycle will overlap.
A setting whereby idle cycle insertion is not performed can be made only when RD and CSn do
not change simultaneously, or when it does not matter if they do.
Rev. 5.0, 09/04, page 188 of 978