3069RF-ZTAT Datasheet, PDF (188/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

DRAM access cycle
φ
4)5n
φ
(a) Access to DRAM space with a different row address
CBR refresh cycle
4)5n
φ
(b) CAS-before-RAS refresh cycle
DRCRA write cycle
4)5n
(c) BE bit or RDM bit cleared to 0 in DRCRA
External bus released
φ
4)5n
High-impedance
(d) External bus released
Note: n = 2 to 5
Figure 6.24 RASn Negation Timing when RAS Down Mode is Selected
Rev. 5.0, 09/04, page 166 of 978