3069RF-ZTAT Datasheet, PDF (161/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

6.3.4 Chip Select Signals
For each of areas 0 to 7, the H8/3069R can output a chip select signal (CS₀ to CS₇) that goes low
when the corresponding area is selected in expanded mode. Figure 6.4 shows the output timing of
a CSn signal.
Output of CS₀ to CS₃: Output of CS₀ to CS₃ is enabled or disabled in the data direction register
(DDR) of the corresponding port.
In
the
expanded
modes
with
on-chip
ROM
disabled,
a
reset
leaves
pin
CS
0
in
the
output
state
and
pins CS₁ to CS₃ in the input state. To output chip select signals CS₁ to CS₃, the corresponding
DDR bits must be set to 1. In the expanded modes with on-chip ROM enabled, a reset leaves pins
CS₀ to CS₃ in the input state. To output chip select signals CS₀ to CS₃, the corresponding DDR bits
must be set to 1. For details, see section 8, I/O Ports.
Output of CS₄ to CS₇: Output of CS₄ to CS₇ is enabled or disabled in the chip select control
register (CSCR). A reset leaves pins CS₄ to CS₇ in the input state. To output chip select signals
CS₄ to CS₇, the corresponding CSCR bits must be set to 1. For details, see section 8, I/O Ports.
φ
Address
External address in area n
+5n
Figure 6.4 CSn Signal Output Timing (n = 0 to 7)
When
the
on-chip
ROM,
on-chip
RAM,
and
on-chip
registers
are
accessed,
CS
0
to
CS
7
remain
high. The CS_n signals are decoded from the address signals. They can be used as chip select
signals for SRAM and other devices.
Rev. 5.0, 09/04, page 139 of 978