3069RF-ZTAT Datasheet, PDF (388/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Contention between General Register Write and Compare Match: If a compare match occurs
in the T₃ state of a general register write cycle, writing takes priority and the compare match signal
is inhibited. See figure 9.40.
General register write cycle
T₁
T₂
T₃
φ
Address bus
GR address
Internal write signal
16TCNT
N
N+1
GR
Compare match signal
N
M
General register write data
Inhibited
Figure 9.40 Contention between General Register Write and Compare Match
Rev. 5.0, 09/04, page 366 of 978