3069RF-ZTAT Datasheet, PDF (985/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

D.2 Pin States at Reset
Modes 1 and 2: Figure D.1 is a timing diagram for the case in which RES goes low during an
external memory access in mode 1 or 2. As soon as RES goes low, all ports are initialized to the
input state. AS, RD, HWR, LWR, and CS₀ go high, and D₁₅ to D₀ go to the high-impedance state.
The address bus is initialized to the low output level 2.5 φ clock cycles after the low level of RES
is sampled. Clock pin P6₇/φ goes to the output state at the next rise of φ after RES goes low.
P6₇/φ
Access to external
memory
T1
T2
T3
RES
Internal reset
signal
A₁₉ to A₀
H'00000
CS₀
AS, RD
(read)
HWR, LWR
(write)
D₁₅ to D₀
(write)
High impedance
I/O port,
CS₇ to CS₁
High impedance
Figure D.1 Reset during Memory Access (Modes 1 and 2)
Rev. 5.0, 09/04, page 963 of 978