3069RF-ZTAT Datasheet, PDF (11/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

5.2 Register Descriptions ........................................................................................................ 86
5.2.1 System Control Register (SYSCR) ...................................................................... 86
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)............................................. 87
5.2.3 IRQ Status Register (ISR).................................................................................... 94
5.2.4 IRQ Enable Register (IER) .................................................................................. 95
5.2.5 IRQ Sense Control Register (ISCR) .................................................................... 96
5.3 Interrupt Sources............................................................................................................... 97
5.3.1 External Interrupts ............................................................................................... 97
5.3.2 Internal Interrupts ................................................................................................ 98
5.3.3 Interrupt Vector Table ......................................................................................... 98
5.4 Interrupt Operation............................................................................................................ 102
5.4.1 Interrupt Handling Process .................................................................................. 102
5.4.2 Interrupt Sequence ............................................................................................... 107
5.4.3 Interrupt Response Time...................................................................................... 108
5.5 Usage Notes ...................................................................................................................... 109
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction...................... 109
5.5.2 Instructions that Inhibit Interrupts ....................................................................... 110
5.5.3 Interrupts during EEPMOV Instruction Execution.............................................. 110
Section 6 Bus Controller....................................................................................111
6.1 Overview........................................................................................................................... 111
6.1.1 Features................................................................................................................ 111
6.1.2 Block Diagram ..................................................................................................... 113
6.1.3 Pin Configuration................................................................................................. 114
6.1.4 Register Configuration......................................................................................... 115
6.2 Register Descriptions ........................................................................................................ 116
6.2.1 Bus Width Control Register (ABWCR)............................................................... 116
6.2.2 Access State Control Register (ASTCR) ............................................................. 117
6.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 117
6.2.4 Bus Release Control Register (BRCR) ................................................................ 121
6.2.5 Bus Control Register (BCR) ................................................................................ 122
6.2.6 Chip Select Control Register (CSCR).................................................................. 126
6.2.7 DRAM Control Register A (DRCRA) ................................................................. 127
6.2.8 DRAM Control Register B (DRCRB) ................................................................. 129
6.2.9 Refresh Timer Control/Status Register (RTMCSR) ............................................ 131
6.2.10 Refresh Timer Counter (RTCNT)........................................................................ 133
6.2.11 Refresh Time Constant Register (RTCOR) ......................................................... 133
6.2.12 Address Control Register (ADRCR).................................................................... 134
6.3 Operation .......................................................................................................................... 135
6.3.1 Area Division ....................................................................................................... 135
6.3.2 Bus Specifications................................................................................................ 137
6.3.3 Memory Interfaces............................................................................................... 138
6.3.4 Chip Select Signals .............................................................................................. 139
Rev. 5.0, 09/04, page vii of xviii