3069RF-ZTAT Datasheet, PDF (546/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

14.3.3 Data Format
Figure 14.3 shows the smart card interface data format. In reception in this mode, a parity check is
carried out on each frame, and if an error is detected an error signal is sent back to the transmitting
device to request retransmission of the data. In transmission, the error signal is sampled and the
same data is retransmitted if the error signal is low.
No parity error
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Output from transmitting device
Parity error
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
DE
Output from transmitting device
[Legend]
Ds:
Start bit
D0 to D7: Data bits
Dp:
Parity bit
DE:
Error signal
Output from
receiving
device
Figure 14.3 Smart Card Interface Data Format
The operating sequence is as follows.
1. When the data line is not in use it is in the high-impedance state, and is fixed high with a pull-
up resistor.
2. The transmitting device starts transfer of one frame of data. The data frame starts with a start
bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp).
3. With the smart card interface, the data line then returns to the high-impedance state. The data
line is pulled high with a pull-up resistor.
4. The receiving device carries out a parity check. If there is no parity error and the data is
received normally, the receiving device waits for reception of the next data. If a parity error
occurs, however, the receiving device outputs an error signal (DE, low-level) to request
retransmission of the data. After outputting the error signal for the prescribed length of time,
the receiving device places the signal line in the high-impedance state again. The signal line is
pulled high again by a pull-up resistor.
Rev. 5.0, 09/04, page 524 of 978