3069RF-ZTAT Datasheet, PDF (180/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Table 6.7 DRAM Interface Pins
Pin
PB4
PB5
HWR
LWR
CS₂
CS₃
CS
4
CS₅
RD
With DRAM
Designated Name
UCAS
Upper column
address strobe
LCAS
Lower column
address strobe
UCAS
Upper column
address strobe
LCAS
Lower column
address strobe
RAS₂
Row address
strobe 2
RAS₃
Row address
strobe 3
RAS
4
Row address
strobe 4
RAS₅
Row address
strobe 5
WE
Write enable
P80
RFSH
A₁₂ to A₀ A₁₂ to A₀
Refresh
Address
D₁₅ to D₀ D₁₅ to D₀
Data
Note: * Fixed high in a read access.
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
I/O
Function
Upper column address strobe for DRAM
space access (when CSEL = 0 in DRCRB)
Lower column address strobe for DRAM
space access (when CSEL = 0 in DRCRB)
Upper column address strobe for DRAM
space access (when CSEL = 1 in DRCRB)
Lower column address strobe for DRAM
space access (when CSEL = 1 in DRCRB)
Row address strobe for DRAM space
access
Row address strobe for DRAM space
access
Row address strobe for DRAM space
access
Row address strobe for DRAM space
access
Write enable for DRAM space write
access*
Goes low in refresh cycle
Row address/column address multiplexed
output
Data input/output pins
6.5.6 Basic Timing
Figure 6.18 shows the basic access timing for DRAM space. The basic DRAM access timing is
four states: one precharge cycle (T_p) state, one row address output cycle (T_r) state, and two column
address output cycle (T_c1, T_c2) states. Unlike the basic bus interface, the corresponding bits in
ASTCR control only enabling or disabling of wait insertion between T_c1 and T_c2, and do not affect
the number of access states. When the corresponding bit in ASTCR is cleared to 0, wait states
cannot be inserted between T_c1 and T_c2 in the DRAM access cycle.
If a DRAM read/write cycle is followed by an access cycle for an external area other than DRAM
space when HWR and LWR are selected as the UCAS and LCAS output pins, an idle cycle (Ti) is
inserted unconditionally immediately after the DRAM access cycle. See section 6.9, Idle Cycle,
for details.
Rev. 5.0, 09/04, page 158 of 978