3069RF-ZTAT Datasheet, PDF (561/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Frame n
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Retransmitted frame
Frame n+1
(DE)
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4
RDRF
[2]
[4]
PER
[1]
[3]
Figure 14.12 Retransmission in SCI Receive Mode
• Retransmission when SCI is in Transmit Mode
Figure 14.13 illustrates retransmission when the SCI is in transmit mode.
6. If an error signal is sent back from the receiving device after transmission of one frame is
completed, the ERS bit is set to 1 in SSR. If the RIE bit in SCR is set to the enable state, an
ERI interrupt is requested. The ERS bit should be cleared to 0 in SSR before the next parity bit
sampling timing.
7. The TEND bit in SSR is not set for the frame for which the error signal was received.
8. If an error signal is not sent back from the receiving device, the ERS flag is not set in SSR.
9. If an error signal is not sent back from the receiving device, transmission of one frame,
including retransmission, is assumed to have been completed, and the TEND bit is set to 1 in
SSR. If the TIE bit in SCR is set to the enable state, a TXI interrupt is requested. If TXI is
enabled as a DMA transfer activation source, the next data can be written in TDR
automatically. When the DMAC writes data in TDR, the TDRE bit is automatically cleared to
0.
Frame n
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Retransmitted frame
(DE)
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Frame n+1
Ds D0 D1 D2 D3 D4
TDRE
Transfer from TDR to TSR
TEND
ERS
Transfer from TDR to TSR
Transfer from TDR to TSR
[7]
[9]
[6]
[8]
Figure 14.13 Retransmission in SCI Transmit Mode
Support of Block Transfer Mode: The smart card interface of this LSI supports an IC card
(smart card) interface corresponding to T=0 (character transfer) in ISO/IEC 7816-3.
Rev. 5.0, 09/04, page 539 of 978