3069RF-ZTAT Datasheet, PDF (169/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

8-Bit, Two-State-Access Areas
Figure 6.10 shows the timing of bus control signals for an 8-bit, two-state-access area. The upper
data bus (D₁₅ to D₈) is used in accesses to these areas. The LWR pin is always high. Wait states
cannot be inserted.
φ
Address bus
CSn
AS
RD
Read access D15 to D8
D7 to D0
HWR
Write access
LWR
D15 to D8
D7 to D0
Bus cycle
T1
T2
External address in area n
Valid
Invalid
High
Valid
Undetermined data
Note: n = 7 to 0
Figure 6.10 Bus Control Signal Timing for 8-Bit, Two-State-Access Area
Rev. 5.0, 09/04, page 147 of 978