3069RF-ZTAT Datasheet, PDF (303/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

8.9.2 Register Descriptions
Table 8.13 summarizes the registers of port 8.
Table 8.13 Port 8 Registers
Address* Name
Abbreviation R/W
H'EE007 Port 8 data direction P8DDR
W
register
H'FFFD7 Port 8 data register P8DR
R/W
Note: * Lower 20 bits of the address in advanced mode.
Initial Value
Modes 1 to 4 Modes 5 and 7
H'F0
H'E0
H'E0
H'E0
Port 8 Data Direction Register (P8DDR): P8DDR is an 8-bit write-only register that can select
input or output for each pin in port 8.
Bits 7 to 5 are reserved. They are fixed at 1, and cannot be modified.
Bit
7
6
5
4
3
2
1
0
—
—
— P8₄DDR P8₃DDR P8₂DDR P8₁DDR P8₀DDR
Modes ^{Initial value 1}
1
1
1
0
0
0
0
1 to 4 _{Read/Write —}
—
—
W
W
W
W
W
Modes ^{Initial value 1}
1
1
0
0
0
0
0
5 and 7 _{Read/Write —}
—
—
W
W
W
W
W
Reserved bits
Port 8 data direction 4 to 0
These bits select input or
output for port 8 pins
Modes 1 to 5 (Expanded Modes): When bits in P8DDR bit are set to 1, P8₄ to P8₁ become CS₀ to
CS₃ output pins. When bits in P8DDR are cleared to 0, the corresponding pins become input ports.
However, P8₁ can also be used as an output port, depending on the setting of bits DRAS2 to
DRAS0 in DRAM control register A (DRCRA). For details see section 6.5.2, DRAM Space and
RAS Output Pin Settings.
In modes 1 to 4 (expanded modes with on-chip ROM disabled), following a reset P8₄ functions as
the CS₀ output, while CS₁ to CS₃ are input ports. In mode 5 (expanded mode with on-chip ROM
enabled), following a reset CS₀ to CS₃ are all input ports.
When the refresh enable bit (RFSHE) in DRCRA is set to 1, P8₀ is used for RFSH output. When
RFSHE is cleared to 0, P8₀ becomes an input/output port according to the P8DDR setting. For
details see table 8.14.
Rev. 5.0, 09/04, page 281 of 978