3069RF-ZTAT Datasheet, PDF (392/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Contention between General Register Write and Input Capture: If an input capture signal
occurs in the T₃ state of a general register write cycle, input capture takes priority and the write to
the general register is not performed. See figure 9.44.
General register write cycle
T₁
T₂
T₃
φ
Address bus
GR address
Internal write signal
Input capture signal
16TCNT
M
GR
M
Figure 9.44 Contention between General Register Write and Input Capture
Rev. 5.0, 09/04, page 370 of 978