3069RF-ZTAT Datasheet, PDF (425/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

10.7 Usage Notes
Note that the following kinds of contention can occur in 8-bit timer operation.
10.7.1 Contention between 8TCNT Write and Clear
If a timer counter clear signal occurs in the T₃ state of a 8TCNT write cycle, clearing of the
counter takes priority and the write is not performed. Figure 10.18 shows the timing in this case.
8TCNT write cycle
T1
T2
T3
φ
Address bus
8TCNT address
Internal write signal
Counter clear signal
8TCNT
N
H'00
Figure 10.18 Contention between 8TCNT Write and Clear
Rev. 5.0, 09/04, page 403 of 978