3069RF-ZTAT Datasheet, PDF(257/1003 Page) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

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3069RF-ZTAT Datasheet, PDF (257/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

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7.4.8 DMAC Bus Cycle

Figure 7.13 shows an example of the timing of the basic DMAC bus cycle. This example shows a

word-size transfer from a 16-bit two-state access area to an 8-bit three-state access area. When the

DMAC gets the bus from the CPU, after one dead cycle (Td), it reads from the source address and

writes to the destination address. During these read and write operations the bus is not released

even if there is another bus request. DMAC cycles comply with bus controller settings in the same

way as CPU cycles.

CPU cycle

DMAC cycle (1 word transfer)

CPU cycle

Ï

Address

bus

RD

T1 T2 T1 T2 Td T1 T2 T1 T2 T3 T1 T2 T3 T1 T2 T1 T2

Source

address

Destination address

HWR

LWR

Figure 7.13 DMA Transfer Bus Timing (Example)

Rev. 5.0, 09/04, page 235 of 978

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