3069RF-ZTAT Datasheet, PDF (714/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

V_CC
56*; ^VIH
EXTAL
φ (internal or
external)
4-5
t_DEXT
Figure 19.7 External Clock Output Settling Delay Timing
19.3 Duty Adjustment Circuit
The duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to
generate φ.
19.4 Prescalers
The prescalers divide the system clock (φ) to generate internal clocks (φ/2 to φ/4096).
19.5 Frequency Divider
The frequency divider divides the duty-adjusted clock signal to generate the system clock (φ). The
frequency division ratio can be changed dynamically by modifying the value in DIVCR, as
described below. Power consumption in the chip is reduced in almost direct proportion to the
frequency division ratio. The system clock generated by the frequency divider can be output at the
φ pin.
Rev. 5.0, 09/04, page 692 of 978