3069RF-ZTAT Datasheet, PDF (215/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

6.11 Register and Pin Input Timing
6.11.1 Register Write Timing
ABWCR, ASTCR, WCRH, and WCRL Write Timing: Data written to ABWCR, ASTCR,
WCRH, and WCRL takes effect starting from the next bus cycle. Figure 6.49 shows the timing
when an instruction fetched from area 0 changes area 0 from three-state access to two-state access.
T1
T2
T3
T1
T2
T3
T1
T2
φ
Address bus
3-state access to area 0
ASTCR address
2-state access to area 0
Figure 6.49 ASTCR Write Timing
DDR and CSCR Write Timing: Data written to DDR or CSCR for the port corresponding to the
CSn pin to switch between CSn output and generic input takes effect starting from the T₃ state of
the DDR write cycle. Figure 6.50 shows the timing when the CS₁ pin is changed from generic
input to CS₁ output.
T1
T2
T3
φ
Address bus
+51
P8DDR address
High-impedance
Figure 6.50 DDR Write Timing
Rev. 5.0, 09/04, page 193 of 978