3069RF-ZTAT Datasheet, PDF (385/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

9.6 Usage Notes
This section describes contention and other matters requiring special attention during 16-bit timer
operations.
Contention between 16TCNT Write and Clear: If a counter clear signal occurs in the T₃ state of
a 16TCNT write cycle, clearing of the counter takes priority and the write is not performed. See
figure 9.37.
16TCNT write cycle
T₁
T₂
T₃
φ
Address bus
16TCNT address
Internal write signal
Counter clear signal
16TCNT
N
H'0000
Figure 9.37 Contention between 16TCNT Write and Clear
Rev. 5.0, 09/04, page 363 of 978